美国Keithley仪器公司的半导体事业部，
演讲人：赵月刚
职务：首席高级应用工程师
Yuegang, Zhao

- Lead Applications Engineer

- 电话：021-62898246

- 电子邮箱：yzhao@keithley.com

赵月刚先生1997年毕业于北京大学，获物理学本科学位；后赴美，于2000年毕业于麦迪逊市的Wisconsin大学，获半导体物理硕士学位，后又于2005年获得Case Western Reserve大学MBA学位。

赵月刚先生于2001年加入了美国Keithley仪器公司的半导体事业部，目前是该部门的首席高级应用工程师。在过去的5年中，他先后与多家全球技术领先的半导体制造公司和行业协会在半导体器件特性分析和可靠性测试技术方面进行过合作，包括使用射频 CV技术对极薄栅氧化层进行特性分析，多点并行NBTI测试和对采用高K材料的FET和SOI器件进行脉冲式I-V特性分析。在过去的两年中，他编写及合作编写了超过15篇技术文章，分别发表在技术刊物、杂志和学术会议上，并且在许多公开研讨会（美国、欧洲与亚洲各地）及网络研讨会上做过不同主题的报告。他有两项脉冲式I-V测试技术的成果已经申请专利

Yuegang Zhao received his MBA from Case Western Reserve University (2005), M.S. in Semiconductor Physics from the University of Wisconsin, Madison (2000), and his B.S. in Physics from Peking University, Beijing, China (1997). He joined the Semiconductor Business Group of Keithley Instruments Inc. in 2001 and currently is a lead applications engineer. He has collaborated in the past 5 years with many major semiconductor manufacturing companies and industry consortiums on various device characterization and reliability test techniques, including ultra-thin gate oxide characterization using RF CV techniques, multi-site parallel NBTI testing with minimized relaxation, and pulse I-V characterization of FETs with high K gate and SOI devices. He has authored and co-authored more than 15 publications in the past two years in technical journals, magazines and conferences and given many public and web seminars on various topics. He has 2 patents pending on pulse I-V test techniques.

先进半导体技术中的最新可靠性问题与测试解决方案

Exploring emerging reliability concerns for advanced CMOS technologies
This technical seminar offers insight to stress induced oxide charge change at Si/Gate dielectrics interface or inside gate material and its links to emerging device reliability issues such as NBTI and Charge Trapping in high K film. Typical gate oxide charge characterization techniques, including characterizing interface trap charge and bulk charge, such as SILC, CV, charge pumping, single pulse charge trapping and ultra-short pulse I-V technique, are described in detail and their applications are explored to explain NBTI degradation and recovery mechanism for PMOSFET and charge trapping phenomena in high K gate dielectrics.

The following topics will be covered in this seminar:
·1. Common interface trap characterization techniques
·2. Issues and findings regarding NBTI degradation and recovery mechanism
·3. Issues and findings regarding charge trapping in high K gate dielectrics
·4. How interface trap characterization techniques used to allow better understanding of NBTI and charge trapping
·5. Introducing pulse into reliability tests
·6.A reliability solution Keithley instruments offers for helping better understand these emerging reliability issues

本次先进半导体技术研讨会的主题是最新出现的可靠性问题以及我们所做的一些解决这些难题的探索与实践。主要介绍了电压应力（stress）导致的在硅/门电介质界面或在门材料内部氧化层电荷的变化，而这些电荷的变化与新器件的可靠性问题直接关联，比如NBTI和高K薄膜中的电荷陷阱。在研讨会中将详细论述典型的门氧化层电荷，包括界面陷阱电荷和门材料内部电荷的特性分析技术，如SILC, CV,电荷泵,单脉冲电荷陷阱和超短脉冲I-V技术，展示它们的应用以揭示NBTI退化和恢复机制，并介绍如何测试高K门电介质中的电荷陷阱现象。
本次研讨会将讨论下列主题：
· 普通界面陷阱特性分析技术
· 关于NBTI退化和恢复机制的问题
· 关于高K门电介质中的电荷陷阱的问题
· 如何使用界面陷阱特性分析技术来更好的理解NBTI和电荷陷阱
· 将脉冲引入可靠性测试
· Keithley仪器公司提供的可靠性测试解决方案，更好地理解这些新出现的可靠性问题。