James Liu 刘钧

Dr. James Liu has over 13 years of experience in the semiconductor industry including management, customer support, process development and integration, device testing, yield and excursion management, product procurement and technology enabling.

James is currently the Chief Technologist at Novellus Systems. He manages the Advanced Technologies and Process Service department in China. He is an expert in Cu-low k process Integration and has worked with wafer manufacturers worldwide to solve Cu-low k issues. Prior to Novellus, he worked over 8 years at Intel Corp. in various technical and managerial positions. His experienced reached a wide range of expertise including technology development and enabling, electrical testing and excursion control system management, and product testing and validation. Prior to leaving for Novellus, he was the program manager responsible in charge of Intel 3rd party memory procurement and technology enabling. He holds a Ph.D degree in Materials Science and Engineering from Cornell University and B.S. degree in Physics from Peking University.

Status and Directions for Cu/Low k interconnects
James Liu
Novellus Systems, Inc.

The transition from aluminum to copper interconnects for integrated circuit applications is already completed with 90nm logic technology node ramped into volume manufacturing. Memory devices are expected to follow at later nodes. Concomitant with the shift to a lower resistivity conductor, lower permittivity (low k) dielectrics has also been adapted as the dielectrics of the choice at the 90nm node in order to reduce both RC delay and crosstalk. The integration of these new conductor and dielectric materials, within the framework of aggressively scaled feature size, presents a formidable challenge which has led to delays in the implementation of low k materials and required new reliability learning for Cu metalization systems. While Cu/low k interconnects have moved into manufacturing, the drive to ramp yield has presented a new set of challenges that dictate the needs for improved process control and robust integration schemes. The subtleties of Cu/low k processing have fostered closer collaboration between semiconductor manufacturers and equipment suppliers, as they strive to meet technology and manufacturing goals. This presentation will provide an overview of the material and process issues that have been confronted and resolved in the implementation of Cu/low k interconnects. The impact of future scaling and materials requirements will also be discussed, along with potential technology solutions.